The downlink of high speed downlink packet access (HSDPA) for third generation partnership project (3GPP) compliant systems tends to suffer from multi-path and requires the use of a chip level equalizer instead of a conventional rake receiver architecture used in communication systems such as code division multiple access (CDMA) communication systems. Chip level equalization for HSDPA is typically performed using a time domain filter computation based upon various techniques such as normalized least mean square (NLMS), 2-stage NLMS, Griffith's, pre-filter rake, channel estimation based LMS (CHEST), Fast Fourier Transform (FFT) based minimum mean squared error (MMSE) filter calculation or channel response based minimum output energy (CR-MOE).
HSDPA delivers superior speed, capacity and efficiency improvements. Some advantages to HSDPA include improved spectrum efficiency, improved network capacity, higher peak data rates, and improved allocation of resources.